Microelectronics: Its unusual origin and personality.
Silicon germanium base heterojunction bipolar transistors by molecular beam epitaxy. Graded SiGe base, poly emitter heterojunction bipolar transistors. Profile leverage in a self aligned epitaxial Si or SiGe base bipolar technology. Low temperature operation of Si and SiGe bipolar transistors. Vertical profile optimization of very high frequency epitaxial Si and SiGe base bipolar transistors. An epitaxial emitter cap SiGe base bipolar technology for liquid nitrogen temperature operation. A Watt S band SiGe hetero junction junction bipolar transistor. Carbon doped SiGe heterojunction bipolar transistors for high frequency applications.
A Brief History of the Field 2 11 Lilienfeld Patent, ; O. Heil, British patent number ,, D Khang and MM Atalla. Silicon silicon dioxide field induced surface devices. Solid State Research Conference, Pittsburgh, Nanowatt logic using field effect metal oxide semiconductor triodes MOSTs. P Balk. Surface properties of oxidized germanium doped silicon. Kibbel, and E Kasper. Optical waveguiding in a single crystal layer of germanium silicon grown on silicon. Optics Letters , Materials Science and Engineering B , Amorphous silicon germanium thin film photodetector array.
High mobility p channel metal oxide semiconductor field effect transistor on strained Si. Electron mobility enhancement in strained Si n type metal oxide semiconductor field effect transistors. S Thompson, N. A Brief History of the Field 2 13 High performance 0. Cressler Georgia Institute of Technology Measurement and modeling of high speed semiconductor devices is something that, unfortunately, is rarely discussed in a meaningful manner in the technical literature.
This is a shame. In my experience, robust measurement and modeling, particularly at the extreme levels of performance found in modern SiGe devices, is a fine art, requires extreme dexterity in the laboratory, and getting reliable data, and importantly, a model to fit the data, is often two thirds of the battle for success that may be an understatement! What tricks did they use? How can I do that for myself? One of the unique features of this handbook is that I have attempted to buck this trend and get some experts to talk about the subtle nuances of the measurement and modeling trade.
It is something I am quite proud of, and I suspect will prove to be very useful to practioners. Mijalkovic of Delft University of Technology, two of the most sophisticated SiGe HBT compact models are described in detail, and importantly, also address how one should intelligently use them! Integrated circuit design kits are amazingly sophisticated these days, and S. Singh of IBM Microelectronics.
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Given that the frequency response of state of the art SiGe HBTs has reached unprecedented levels, designers are now beginning to seriously attack microwave and even mm wave applications in SiGe. Tretiakov of RF Micro Devices. Liang of Georgia Tech. Groves IBM Microelectronics 4. C V AC Device Measurement Techniques: Overview Development of high quality device models is an essential ingredient in the design of successful analog and mixed signal applications.
Accurate device characterization plays a critical role in model develop ment and circuit benchmarking. Model behavior must be verified against device measurements in order to validate the model and to define regions outside which the model may be inaccurate. The characterization of high performance silicon heterostructures, and associated passives, requires care due to the demanding requirements associated with these devices: high frequencies, low leakage currents, low resistances, wide temperature ranges, etc.
An area of particular concern and interest to device modelers and circuit designers is the improvement of the S parameter measurement methodology as the measurement frequency extends to GHz and beyond. Traditional calibration and de embedding techniques need to be re examined to determine if the underlying assumptions remain valid [1,2]. In addition to characterization in support of model development, circuits must be measured and compared to design predictions and requirements.
Circuit measurement is particularly demanding for applications utilizing SiGe devices due to the high frequency and low noise characteristics of these designs [3,4]. Frequently, off the shelf measurement solutions do not exist to satisfy the characterization requirements for these cutting edge circuits, requiring circuit designers to assume the role of test system developer. Preceding all these requirements is the necessity to create carefully controlled device measurement test structures that allow for accurate extraction of the desired device and circuit parametrics.
Careful thought must be given to the limitations inherent in creating low parasitic test structures in a wafer probing environment. This includes the creation of additional test structures that allow for the accurate characterization of the test structure parasitics, so that the device characteristics can be accurately de embedded from the measured data [5,6]. Often the linear behavior of the DUT to a test signal is needed in order to characterize or model its behavior.
A test system that is able to accurately report the network parameters of an unknown linear network to an applied signal is required for these high frequency measurements. Some network parameters appropriate to characterization and modeling of silicon heterostructures, passives, and circuits are H parameters hybrid parameters , Y parameters admittance parameters , Z parameters impedance parameters , S parameters scatter ing parameters , and T parameters transmission parameters. Each of these network parameter sets describes the response of the DUT to a defined set of input conditions.
H parameters, for instance, are widely used to determine HBT device characteristics. They are useful for this purpose because the equations describing the H parameters can naturally be used to determine short circuit current gain or b in addition to other useful device parametrics. Network parameters are applicable generally to N port networks. Most applications of network parameters are limited to between two and four port networks. Since many circuits and devices have two well defined ports, two port networks are quite often the most useful in determining DUT characteristics.
The two port network shown in Figure 4. Under conditions of applied stimulus to one of the ports and defined termination of the other port, the response of the network can be characterized in terms of the voltage and current relationships observed at the ports. For a two port network, two equations completely define the network character istics as a function of the applied stimuli and measured voltages and currents and some constants of proportionality simply the network parameters themselves.
Similarly, the other three H parameters can be derived from physical measurements by simply applying the appropriate voltages and currents and setting one of the ports to either an open or short circuit condition as required by the definitions in Equation 4. A problem arises in applying this direct measurement technique at high frequencies. It is difficult to achieve perfect short or open circuits at the device terminals due to the parasitics associated with the connections between the measurement instruments and the device.
These parasitic capacitances, resist ances, and inductances combine to make the characteristics of open and short circuit connections strong functions of frequency. Therefore, a short circuit at one frequency may appear to be an open circuit at another, etc. This makes the broadband, direct measurement of many of the network parameters difficult. Another difficulty comes into play with active devices. Even if perfect broadband open and short circuits were achievable, silicon heterostructures may not be stable under conditions of open and short circuit termination of their terminals due to high gain and low parasitic resistances.
The solution to this dilemma is to make device measurements using a set of network parameters that make use of applied bias and termination conditions that are easily achievable at high frequencies and that lend themselves to stable device operation. S parameters satisfy these requirements. S parameters are defined similarly to the previously described network parameters except that the applied bias conditions are defined in terms of traveling voltage waves, rather than total voltages and currents, and the termination conditions are defined in terms of the characteristic impedance of the transmission lines supplying these traveling waves, rather than open and short circuits.
Figure 4. The traveling voltage wave incident on port 1 will generate a reflected wave traveling back toward the source due to impedance mismatch between port 1 of the DUT and the transmission line. In addition, some of the energy will be transmitted through the network to port 2 and travel down the transmission line toward the load impedance. A voltage wave will then be reflected from the load toward port 2 assuming that the load impedance is not equal to the characteristic impedance of the line , some of which will be transmitted back through the network and travel down the port 1 transmission line toward the generator where it will be either reflected or absorbed.
Further reflections occur as each of these reflected voltage waves encounter an impedance mismatch or discontinuity. This complex combination of forward and reflected waves on the transmission lines connected to ports one and two will generate standing voltage waves. Loss less transmission lines connect the DUT to the applied signal and load termination. This implies that the voltage wave is totally absorbed by a load impedance that is equal to the characteristic impedance of the transmission line.
Thus, the two load conditions that must be achieved in order to directly measure the four S parameters are as follows: 1. A load has been put in place of the generator of Figure 4. The circuit of Figure 4. These load conditions in a typical S parameter measurement system are equal to 50 V, since the transmission lines connecting the measurement instrument and the DUT are generally 50 V transmis sion lines. This condition is much easier to achieve over a broad range of very high frequencies and contributes to a more stable measurement environment for high gain devices.
Measuring the S parameters of a DUT, then, consists of measuring the complex voltage waves present at the DUT ports under the conditions of an applied voltage wave transmitted through a loss less transmission line toward one port and the termination of the other ports with a 50 V load for a 50 V measurement system. While this is simpler than achieving the requirements for directly measuring a set of network parameters defined in terms of total voltages and currents implying that perfect open and short termination conditions must be realized , there are still difficulties in achieving accurate meas urements representative of the conditions at the DUT ports due to nonideal measurement conditions.
For example, the transmission line connecting the measurement instrument and DUT has losses and may not have a Z0 of exactly 50 V, making it nonideal; reflections occur where cables, waveguides, or wafer probes connect to the measurement system and the DUT due to impedance mismatches; the 50 V load termination has frequency dependent behavior and is not exactly 50 V; the generator does not have a perfect 50 V impedance; the equipment required to sample and measure the incident and reflected voltage waves causes additional losses and distortions; when making on wafer measurements, the probe pads and transmission line launches introduce further errors.
The procedures used to extract the DUT port characteristics from the raw measured S parameters are called calibration and de embedding. Instrumentation The measurement of S parameters is most commonly performed using a test instrument called a vector network analyzer VNA. Fully automated VNAs, able to measure more than one port S parameters, typically contain switching elements that allow for either a signal or load to be applied to each port in turn enabling the measurement of the multiport S parameters with no manual intervention.
In addition, a means of calibrating out the parasitics associated with connecting the VNA to a DUT is generally provided as an internal procedure that can be implemented from the instrument front panel or through a network connection by a host computer. Calibration Since all voltage wave measurements must, of necessity, be made in the VNA itself, a means of accounting for the effects of the nonideal transmission lines and other parasitics, present between the VNA measurement transducers and the DUT ports is required.
In the simplest sense, VNA calibration makes use of the concept of a shifted reference plane to enable the direct measurement of the DUT port characteristics. The measurement reference plane defines the actual ports of the uncalibrated, measured S parameters and exists somewhere in the interior of the VNA itself. This implies that 16 error terms the S parameters of the four port matrix S 0 must be determined during calibration in order to fully describe the four port error network.
Once the 16 error terms are known, the DUT S parameters can be extracted from the measured S parameters using matrix manipulation. This means that the eight S parameters representing signal transmission through the network are equal in both the forward and reverse directions i. A reciprocal four port network, then, can be fully qualified with 12 error terms, since four of them will be redundant.
This is, in essence, how the standard VNA 12 term error model is derived . Calibration consists of measuring known standards located at the DUT reference plane and then applying algorithms to determine the 12 error terms. Copyright , Agilent Technologies, Inc. Reproduced with permission of Agilent Technologies. Let the four port error network represent the environment between the VNA and the probe tips. Shift the reference plane to the probe tips followed by an additional step called deembedding that is designed to characterize and remove any additional parasitics that might exist between the probe pads and the DUT.
Shift the reference plane directly to the DUT ports by measuring standards at the end of the signal launches that exist between the probe pads and the DUT. Each approach requires that the 12 unknown error terms be determined to a great degree of accuracy. The first approach requires the additional determination of the parasitic behavior of the probe pads and transmission line launches connecting the probes to the DUT.
Determination of the error terms is done in a similar manner regardless of the desired location of the corrected reference plane. If the reference plane is desired to be at the probe tips method 1 , then the calibration standards may be realized either on wafer or on a separate calibration substrate.
In order to shift the reference plane directly to the DUT ports method 2 , the calibration standards must be realized on wafer, in close proximity to the DUT. There are several different techniques that can be used to achieve the desired reference plane shift, generally named according to the calibration standards required to achieve the calibrations [9,10]:. Requires accurate knowledge of actual characteristics parasitic inductance and capacitance of cal standards up to the highest frequency of operation.
Used successfully to 50 GHz and beyond, but sensitive to probe placement at higher frequencies, making measurement repeatability a problem. Typically used in applications where probes cannot be placed such that they are opposed Best Practice AC Measurement Techniques. Accuracy suffers in relation to SOLT cals . Multiple different line lengths probe spacing variable required to provide broadband calibration i. Characteristic impedance of lines defines reference impedance of resulting S parameters.
Extending frequency range below 5 GHz requires excessively long transmission lines as cal standards and may sacrifice accuracy. Dispersion effects on the transmission line Z0 can limit effectiveness . Thru delay and Match resistance must be known. Match reactance adjusted to achieve best calibrated open response.
Match resistance defines reference impedance of resulting S parameters. Less sensitive to probe placement. While shifting the measurement reference plane directly to the DUT terminals in one step is desirable, in practice this technique is difficult to implement due to problems associated with achieving acceptable calibration standards on wafer. Match standards typically 50 V resistors are difficult to achieve with sufficient tolerance and low parasitics. Off wafer match standards are laser trimmed to within 0. Transmission lines realized on Si wafers display excessive dispersion and loss effects for characteristic impedances near 50 V and for lines long enough to allow for reasonably low frequency measurements.
Additionally, transmission line standards, with sufficient length to allow measurement as low as 5 GHz, require large chip areas due to their excessive length. For these reasons, the first approach mentioned above calibration to probe tips followed by on wafer de embedding is the de facto standard for calibrating on wafer S parameter measurements.
The parasitic capacitance to ground and probe to probe coupling primarily through the substrate experi enced by the probe when measuring the cal standards of the off wafer cal substrate typically an insulating alumina substrate will be different than those seen when probing the DUT on wafer typically lossy Si substrate. This difference will result in systematic errors that will not be accounted for in the probe tip cal.
This systematic error can be minimized through careful measurement structure design. TRL and SOLR calibrations have drawbacks in bandwidth and accuracy that generally preclude their use except in special circumstances. Proper choice of calibration and de embedding techniques, then, is a major factor in achieving accurate S parameter measurements to GHz and beyond. De-Embedding The procedure used most frequently for on wafer de embedding of DUT characteristics from probe tip calibrated measurements makes use of on wafer standards designed to represent the parasitic environ ment around the DUT [13 18].
This layout is optimized for two port probing with ground signal ground GSG microwave probes. The GSG probes provide a means of launching a coplanar voltage wave onto the probe pads from the primarily coaxial transmission environment that exists between the VNA and the probes . The S parameter padset is designed to minimize the parasitic capacitance, resistance, and inductance that will need to be de embedded from the measured S parameters.
The signal pad is made as small as possible while still providing enough metal landing area to completely land the microwave probe tip without overhanging the sides of the pad, as an overhanging probe provides additional parasitic capacitance that must be de embedded. A conductive groundplane 48 Measurement and Modeling of Silicon Heterostructure Devices running from the top ground strap to the bottom ground strap at each port is often provided underneath the signal pad, providing a well defined, low impedance return path for the parasitic electric field of the pad.
This ground return path can be constructed of any material with reasonable conduct ivity, such as silicided polysilicon or a metal layer, such as M1. The various parasitic elements associated with the padset are added to the padset of Figure 4. The schematic representation of the padset parasitics alone can be seen in Figure 4. As can be seen from Figure 4. On the other hand, the network consisting of Z1 and Z2 port to DUT series resistive and inductive parasitics , and the network represented by Z3 DUT third terminal to ground resistive and inductive parasitics are in a series connection with the DUT terminals.
This grouping of the padset parasitics into two networks, Z representing the combined series connected parasitics and G representing those parasitics that show up in parallel with the DUT, allows us to effectively remove or minimize the effects of the parasitics through the procedure called de embedding. Proper design of these standards is crucial to achieving accurate de embedding of the padset parasitics up to very high frequencies.
In order for Open Short de embedding to provide valid results, the padset must be designed to have an electrical behavior that closely mimics the schematic of Figure 4. Any series or parallel paths not accounted for in the schematic should be minimized as much as possible i. If the padset is made to mimic the schematic as closely as possible and the parasitics are reduced to as low a value as possible, Open Short de embedding can provide valid results to GHz.
Above GHz and for padsets that, due to their larger than normal size as in spiral inductors do not adhere to the schematic, further de embedding methods may be required [1,2]. The de embedding procedure consists of the following steps: 1. Measure the S parameters of the Open and Short de embedding standards Sopen and Sshort, respectively. Subtract Yopen from 0 the Y parameters of the short standard with the parallel capacitive and Yshort to yield Yshort resistive contribution from the pads and substrate removed.
Zshort now represents the combined network consisting of the three 4. Convert Yshort series impedances Z1, Z2, and Z3. Convert Smeas to Ymeas and subtract Yopen from it. This yields Ymeas with the parallel capacitive and resistive contribution from the pads and substrate removed. Subtract Zshort 00 00 back into fully padset corrected S parameters Smeas padset parasitics and finally, convert Zmeas for analysis of the DUT terminal characteristics.
In addition to creating an ideal padset structure, another condition must be satisfied in order to be able to achieve valid results from Open Short de embedding. This is not a problem for the Open and Short standards, as they are passive networks and, therefore, satisfy the LTI requirements. This condition holds true when the input power level is low enough to ensure that the device gain remains linear with input power.
Above this threshold input power level, the device no longer behaves as an LTI system, and the de embedding procedures are no longer valid. For example, if the device cannot linearly translate the input to the output i. This concept applies to all four S parameters, not just S If a particular S parameter changes significantly with varying power level, the device can be said to be operating nonlinearly, negating the validity of the S parameters.
A simple test for this is to display the S parameter of interest while the device is biased in its operational region. Divide the display data, using the VNA display math functions, by itself to yield a flat curve with a value of 0 dB across the frequency range of interest. Next change the power level in stages and observe the resulting curve. At some point the curve will begin to deviate from a flat 0 dB line. The magnitude of this deviation in dB is a measure of the nonlinearity of the device at that power level.
For a range of power levels, there will exist a power level below which the S parameters will no longer change. This is the highest power level that should be applied to the device while still assuring linear behavior. Power levels significantly below this level should be avoided for a different reason. The VNA has a noise floor that is a function of various settings and the internal instrumentation itself, the dynamic range of the VNA measurement is the difference between the measured power level and the noise floor. A high dynamic range is desired as it implies less noise present in the measured results.
One further caution should be observed with regard to power levels. DUTs with high gain many silicon heterostructures may raise the output power level enough to overload the receiver on the input of the VNA. Judicious choice of input power levels, and possibly attenuation on the output, should be used to avoid this overload condition, which will affect the accuracy of the measured results. Therefore, appropriate choice of measurement power level is critical to achieving accurate S parameters for silicon heterostructures.
Some incorrect power conditions will be obvious i. C—V For certain measurement situations, determination of device capacitance or inductance through S parameter measurements is not required. Capacitance and inductance characteristics versus voltage or current bias can be achieved through the use of an impedance measurement system.
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This method is only suitable for measuring device characteristics that can be well described by a simple model consisting of resistors, capacitors, and inductors in various series and parallel configurations. The instrument essentially measures the magnitude and phase response of the DUT to an applied AC and DC bias frequencies typically less than 10 MHz and then applies a model i. Different models will be appropriate for different device characteristics. For example a large capacitor with a nonnegligible series resistance might benefit from extracting the capacitance and resistance from a series R C model.
The model is typically chosen such that the reactive component characteristics can be extracted from the imaginary part of the measured impedance without having a strong variation in value over a certain range of frequencies. Different models may be appropriate for the same device at different measurement frequencies.
Proper selection of the measurement model and frequency of measurement is crucial to getting meaningful data from an impedance measurement system . A basic understanding of S parameters and the role they play in determining device and circuit characteristics is important for the laboratory technician, device development engineer, device modeler, and circuit designer. Proper interpretation of S parameter and low frequency C V measurement data provides the engineer with the information needed to make informed decisions in the technology development and product design processes.
An understand ing of the assumptions used in the calibration, de embedding and reporting of high frequency data allows the engineer to use the information wisely, discarding information that may be based on invalid assump tions. This chapter has attempted to lay the groundwork for interpreting high frequency data acquired in the RF laboratory. In addition some effort has been made to describe the requirements for creating effective on wafer measurement pad structures that minimize the parasitics that must be de embedded from measured data. Properly designed pad structures allow for more accurate de embedding of measured device characteristics, resulting in data that accurately represent the DUT terminal characteristics.
Liang, J. Cressler, G. Niu, Y. Lu, G. Freeman, D. Ahlgren, R. Malladi, K. Newton, and D. A simple 4 port parasitic de embedding methodology for high frequency character ization of SiGe HBTs. Tiemeijer, J. Ramon, and Havens. A calibrated lumped element de embedding technique for on wafer RF characterization of high quality inductors and high speed transistors. Kim, J. Plouchart, N. Zamdmer, N. Fong, M.
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Talbi, R. Trzcinski, J. Safran, K. Wu, S. Womack, J. Sleight, C. Sheraw, A. Ray, and L. Freeman, M. Meghelli, Y. Kwark, S. Zier, A. Rvlyakov, M. Sorna, T. Tanji, O. Schreiber, K. Walter, J. Rieh, B. Jagannathan, A. Joseph, and S. Shield based microwave on wafer device measurements. Kolding, O. Jensen, and T. Agilent Technologies, Inc. Applica tion Note, Application Note, Cascade Microtech, Inc. Safwat and L.
Sensitivity analysis of calibration standards for fixed probe spacing on wafer calibration techniques. Basu and L. Walters, R. Pollard, J. Richardson, and B. The effects of process variations on microstrip wafer calibration. Koolen, J. Geelen, and M. An improved de embedding technique for on wafer high frequency characterization. Cho and D. A three step method for the de embedding of high frequency S parameter Measurements.
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Selected topics in RF coplanar probing. AC Extraction and Calibration.
Advanced RF Simulations 5. The capability to perform numerical process and device simulation that is able to accurately predict device performance under various process conditions can significantly reduce the time and cost of technology development. With experimental wafer processing costs increasing dramatically for advanced generation technologies, the economic necessity for accurate predictive TCAD is apparent.
But it is not only the wafer cost and device complexity that is continuing to drive the need for accurate predictive SiGe TCAD. Unlike the high performance CMOS logic that can have years between products, the analog and mixed signal market that encompasses the majority of SiGe applications demands significantly reduced product cycle time. This aggressive development schedule is generating a new paradigm for the relationship between TCAD, process development, and circuit designers.
The flow is then iterated until target device characteristics are achieved and representative hardware can be furnished to the compact modeling team. The compact modeling team must then fully characterize the devices to generate a physically based model parameter set, which is then combined with the complete technology design kit. Even if the process of record is known, circuit designers cannot begin to design for a significant period of time before the processing, characterization, and design kit cycle is complete. It is in this regard that TCAD can be used to impact the product design cycle time independent of the benefits contributed by increased process development time Figure 5.
A compact model can then be provided to circuit designers in substantially earlier timeframe than traditionally available, based on calibrated physical simulations. As the technology development progresses, updates to the compact models can be provided to ensure the designers will have minimal design impact from the initial models to the final hardware based models. The following sections demonstrate this new methodology with an overview of the TCAD process, device, and compact modeling strategy successfully employed in developing state of the art SiGe technologies.
The incorporation of models that account for the co diffusion of point defects interstitials and vacancies with dopant impurities addressed the important physical effects of oxidation enhanced diffusion and transient enhanced diffusion, forming the basis for the impurity diffusion models used in modern silicon process simulation programs.
Such programs combine many different physical modeling capabilities including oxidation, diffusion of various dopants and their interactions, etching, deposition, and various approaches to simulating ion implantation. In the following discussion, it is assumed that the goal is not merely to generate an idealized SiGe HBT structure, for which task detailed process simulation is not required, but rather to address the issue that dominates practical industrial applications of process and device simulation for SiGe BiCMOS technologies. Issues related to lateral diffusion of impurities generally dominate CMOS process simulation devel opment, and the resultant physical models are equally applicable to issues related to vertical impurity diffusion profiles critical to SiGe HBT simulation.
Emitter Out-Diffusion Polysilicon is generally used to form the emitter region of modern high speed SiGe HBTs as the polysilicon has a significantly lower surface recombination velocity to maintain high current gain with the continually scaled emitter diffusion depths. The emitter polysilicon is generally formed by a low temperature epitaxial process to reduce thermal effects on existing CMOS components, with impurities added either in situ during epitaxy or by ion implantation.
The subsequent annealing and out diffusion of the emitter dopants into the SiGe epitaxy creates the HBT emitter base region.
This positioning of the intersection of the emitter diffusion with germanium profile and both intrinsic and extrinsic base regions is fundamental in determining the transistors DC and AC characteristics. This annealing and out diffusion of the emitter dopants, and their impact on the other dopant profiles under the emitter, is a complex combination of physical phenomena. Process dependent physical effects such as arsenic As or phosphorus P deactivation mechanisms between As or P and vacancies, diffusion of dopants through interfacial oxide layers between the polyemitter and silicon, As or P clustering mechanisms, and diffusion differences of As or P in Si and strained or relaxed SiGe must be considered in the process simulation modeling to predictively fit the As or P emitter out diffused profiles.
Because of this complexity, TCAD cannot expect to be predictive over wide variations in process conditions by assuming diffusion models characteristic of CMOS technology development. Figure 5. The arsenic distribution in the emitter can be divided into four distinct regions. In the first region a relatively uniform distribution of arsenic in deposited polycrystalline emitter, which can be calibrated based on process knowledge or testing of emitter sheet resistance structures. Second, the region where there is an As dopant segregation at the poly silicon Si interface is calibrated using SIMS information and tuning the segregation and transport coefficients between polycrystalline emitter and single crystalline silicon.
The third and fourth regions consist of the As diffusion regions in the pure Si cap and the strained SiGe epitaxial layers, respectively. Full model is the simulated As out diffused profile from polysilicon emitter considering As diffusion difference in Si and strained SiGe epitaxial layers and clustering between and As and B atoms.
The individual contributions may require significant tuning of the large number of various parameters during process simulations in order to be predictive over a wide range of processing conditions. Point defects flow through the base as a result of P and As out diffused from the subcollector, emitter diffusions, extrinsic base implants, and selectively implanted collector SIC implants, all of which influence the boron diffusion in the intrinsic base. Although point defect interaction with boron is typically considered in CMOS process simulation, in the SiGe or SiGeC base both the Ge and C concentrations have a strong influence in the base diffusion mechanics, and must be considered if a useful range of predictive simulation is expected.
Two approaches to simulating the HBT vertical profile are typically used. The first approach illustrated in Figure 5. Solid State Electron.
With permission. For SiGe:C profiles, the more complex, yet potentially more predictive approach, is to individually treat both the Ge and C influence on the B diffusivity. It is well known that C controls the B diffusivity in SiGe:C base by trapping the interstitials , while the Ge concentration affects the B diffusion by both strain and Ge:B clustering mechanisms .
For modeling purposes, difficulties arise in separating the individual contributions from the Ge and C on the B diffusion, especially since the effects contain the forward and reverse GeB clustering reactions and the forward and reverse C trapping of interstitials. Careful tuning of both forward and reverse reaction coefficients with the previous B diffusivity variables is required for predictive models.
These final process variables consist of a careful balance between the Ge and C impact on the base B diffusion. This simulated device structure can either be directly used as input for device simulation, or translated through a regridding procedure, resulting in a more robust device simulation grid. The SiGe HBT grid generation benefits from the central role played by epitaxy in the process simulation.
Since epitaxy models typically consist of repeated depositions of thin layers of material, the mesh arising from the process simulation will contain a smooth, finely graded grid point distribution in the device active areas. Experience has shown that such grids can serve as excellent device simulation platforms with minimal adjustment. For HBT device simulation, the fundamental electrical and material properties of the SiGe layers must also be accurately captured through the physical device models in the device simulator.
For SiGe devices, the most fundamental changes to the default Si models pertain to the rigid bandgap narrowing and the mobility models for the minority and majority carriers. Distortion of the band structure due to the Ge induced stress causes a change in the effective mass and consequently carrier mobilities. Low field mobilities for both electrons and holes are equally important in bipolar device operation and must be accurately modeled in the device simulator.
Experimental measurements, analytical models, and Monte Carlo simulations given in Refs. The mobility model given in Ref. Inclusion of the permittivity changes with Ge content is important for internal electric field and capacitance calculations. The collector current calibration is predominantly dependent on the accuracy of the process emitter diffusion into the Ge and base profiles in combination with the bandgap narrowing models.
Since the carrier properties at the emitter base interface are strongly dependent on the interface processing conditions, polysilicon grain size, and impurity concentration, liberal adjustment to the emitter minority carrier poly silicon lifetimes are used to accurately match the experimental base currents.
Extrinsic resistances that account for contact resistances and technology dependent polysilicon resistances must be added only as needed depending on the comprehensiveness of the process simulation. Optimizations of layout variables such as collector contact configuration and isolation trench design require full two dimensional process and device simulation of both the intrinsic and extrinsic device regions. Reliable numerical simulation of such events is challenging, especially for modern high performance HBTs, which rely on very nonuniform and relatively heavily doped collector and base regions to achieve performance targets.
For HBT breakdown simulations, local field models can perform adequately for high power transistors with wide, low doped collector regions. For more complex devices, experience has shown that hydrodynamic models  can reliably simulate HBT breakdown modes. The simulation user should expect to be prepared to tune critical parameters for such models, such as energy relaxation times and impact ionization thresholds, in the calibration phase of such modeling.
Example simulation versus hardware plots of both ft and fmax are shown in Figure 5. The simulated S parameters can not only be used to extract ac performance metrics such as ft and fmax, but also used to extract important information on the accuracy of individual calibration para meters such as rb, Ccb, Cbe, etc. Practical ac experimental characterization methods, such as extraction of base and emitter resistance using the impedance circle method and extraction of total junction capacitances using cold S parameter simulations, can be applied to simulated data for a direct calibration of intrinsic components.
Advanced RF Simulations For RF applications, advanced simulations of high frequency noise as well as intermodulation charac teristics may be useful in the intrinsic device design phase but are often not considered necessary for predictive modeling. RF noise simulations are possible using impedance field methods  or hierarchal DD and HD methods from Monte Carlo simulations , but with results that are generally useful for only qualitative investigation of gross noise source phenomenon.
Similarly, simulation of distortion through harmonic balance based methods  can prove to be informative for device design in determining the major components of nonlinearities that can affect important RF power metrics such as IIP3. However, these performance metrics can also be much more easily obtained through circuit simulation of the extracted compact model parameters from the simulated device characteristics.
The thickness of this spacer is critical in determining the inherent tradeoff between the fT and fmax of the device. If the spacer is too thin, extrinsic base implants will diffuse far into the intrinsic base region resulting in an increased base transit time, and lowering fT, but also favorably decreasing base resistance and increasing fmax.
On the other hand, increasing the spacer has a positive effect on fT, but ultimately increases the base link resistance and lowers the peak fmax. Through full two dimensional calibrated process simulation experiments and device simulations, an optimal spacer thickness was determined and resulted in a fT increase of 10 GHz through the extrinsic base process redesign.
The simulations were used not only to maximize fT, but also to establish the sensitivity of fT to potential process variances.
In order to increase the 90 GHz device to GHz, an extensive device redesign that targeted the entire intrinsic device including the trapezoidal germanium profile as well as the as deposited intrinsic 59 Industrial Application of TCAD for SiGe Development 0. These modifications in turn drove changes to the collector design to maximize the transit time reduction offered by the redesign of the intrinsic base, since without modifications to the collector, reduced the reduced base transit time benefits may be negated by corresponding increases in collector transit times with an earlier onset of Kirk effect.
Experimental fT and fmax results, shown in Figure 5. These optimizations of peak device performance have always been the main object of TCAD, but for manufacturing purposes, sensitivity of the design point to process changes can be of equal priority. If the targeted design point is too sensitive to process variation, product yield and profitability can suffer, but it is often expensive and time consuming to produce large amounts of process window hardware during the development process.
These tasks can be efficiently handled by well calibrated two dimensional device simulations. But since the previously described approach to TCAD simulation encompasses the complete process and device simulation, it is elementary to produce the entire suite of ac and dc device characteristics that are needed to extract a suitable model for circuit design. Generating the compact model can be difficult and time consuming due to the amount of required data and number of modeling parameters. Results of a simulated design of experiments showing process sensitivity of two optimized design 0.
Genetic algorithms have many advantages over more familiar optimization approaches, in particular robustness to getting caught in local minima, no requirements on calculation of functional derivatives or solution of large sets of linear equations, and easy specification of variable constraints. This significantly reduces the extraction and optimization effort as well as eliminating inaccuracies resulting from commonly used fitting methods to approximate model equations, allowing designers early access to technology models.
As developmental wafer costs and process cycle are driven to more aggressive schedules, industry will continue to leverage TCAD as a core component of SiGe technology development. RB Fair. Explanation of anomalous base regions in transistors. Arsenic deactivation enhanced diffusion: a time, temperature, and concentration study.
Comparison of arsenic and phosphorus diffusion behavior in silicon germanium alloys. Diffusion in strained Si Ge. K Rajendran and W Schoenmaker. Suppressed diffusion of boron and carbon in carbon rich silicon. Modeling the suppression of boron transient enhanced diffusion in silicon by subtitutional carbon incorportation.
IEEE Trans. Electron Dev. V Palankovski and S. Critical modeling issues of SiGe semiconductor devices. Comprehensive hydrodynamic simulation of an industrial SiGe heterobipolar transistor. Techniques for small signal analysis of semiconductor devices. The impedance field method of noise calculation in active semiconductor devices.
New York: Academic Press, Relaxation based harmonic balance technique for semiconductor device simulation. Use of genetic algorithm optimization techniques for bipolar compact modeling. External Base Emitter Region. External Base Collector Region. Collector Substrate Region. This combination of narrow base width, due to epitaxial growth techniques, and lateral footprint reduction, due to the utilization of advanced CMOS lithography, has resulted in a tremendous performance boost of Si based bipolar transistors e.
In order to capture the resulting new electrical and physical effects occurring in such technologies, improved compact models have been developed such as the HIgh CUrrent Model HICUM [2 4], that provide the capability of accurately predicting circuit performance. Thus, saving just one design cycle and its associated mask cost quickly pays off any model development and support cost. The development of sophisticated compact models takes 10 to 20 years before they actually become suitable for production circuit design.
HICUM development started in the early s [5,6], originally targeting the design of high speed fiber optic circuits using geometry scaling for circuit optimization [7,8]. Later on, the model was extended to accurately simulate high frequency small signal operation .
Over time, many effects occurring in advanced Si SiGe heterojunction bipolar transistors HBTs have been added [10 13], and further developments still ongoing following the advancements in bipolar transistor technology and design [36,37]. It should be emphasized that a successful production compact model and its development have to satisfy many requirements from different directions as visualized in Figure 6.
Since such a model embraces a major portion of the respective transistor theory, completely presenting its physical background and the 61 62 Measurement and Modeling of Silicon Heterostructure Devices Process development Include all physical effects Model parameters without wafers Rapid et al. Therefore, the goal of this chapter is to provide an overview on HICUM and its associated infrastructure that needs to be in place to deploy the model for production design purposes.
This includes: i the basic operating principle of HICUM, ii how the physical effects in advanced transistors are covered, iii the geometry scaling methods used, iv the parameter determination methodology, v how a hierarchy of models can be generated in an efficient way, and vi new research directions.
For all the above topics, the reader is guided through the related literature that contains more detailed explanations and background material. Geometry scaling, although required for a model, will be discussed in Section 6. If not otherwise specified, an npn transistor and forward operation is assumed. Note that proper modeling of inverse biasing is still necessary from a simulator point of view. Figure 6. Daub, E. Knabe, S. Accepted by Prog. Fuhs, W. Fuyuki, T. Kirchartz, T. Heidemann, F. D: Appl. Schroder, D. Wiley, New York Google Scholar.
Datta, A. Timoshenko, V. Laades, A. Lumb, M. Academic Press, London Google Scholar. Status Solidi. Main, C. World Scientific, Singapore Google Scholar. Okamoto, H. Kleider, J. In: MRS Symp. Schmidt, M. Korte, L. Ribeyron, P. Kurata, K. Chouffot, R. Science and Eng. Personalised recommendations.
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