Measurement and Modeling of Silicon Heterostructure Devices

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A Brief History of the Field 2 11 Lilienfeld Patent, ; O. Heil, British patent number ,, D Khang and MM Atalla. Silicon silicon dioxide field induced surface devices. Solid State Research Conference, Pittsburgh, Nanowatt logic using field effect metal oxide semiconductor triodes MOSTs. P Balk. Surface properties of oxidized germanium doped silicon. Kibbel, and E Kasper. Optical waveguiding in a single crystal layer of germanium silicon grown on silicon. Optics Letters , Materials Science and Engineering B , Amorphous silicon germanium thin film photodetector array.

High mobility p channel metal oxide semiconductor field effect transistor on strained Si. Electron mobility enhancement in strained Si n type metal oxide semiconductor field effect transistors. S Thompson, N. A Brief History of the Field 2 13 High performance 0. Cressler Georgia Institute of Technology Measurement and modeling of high speed semiconductor devices is something that, unfortunately, is rarely discussed in a meaningful manner in the technical literature.

This is a shame. In my experience, robust measurement and modeling, particularly at the extreme levels of performance found in modern SiGe devices, is a fine art, requires extreme dexterity in the laboratory, and getting reliable data, and importantly, a model to fit the data, is often two thirds of the battle for success that may be an understatement! What tricks did they use? How can I do that for myself? One of the unique features of this handbook is that I have attempted to buck this trend and get some experts to talk about the subtle nuances of the measurement and modeling trade.

It is something I am quite proud of, and I suspect will prove to be very useful to practioners. Mijalkovic of Delft University of Technology, two of the most sophisticated SiGe HBT compact models are described in detail, and importantly, also address how one should intelligently use them! Integrated circuit design kits are amazingly sophisticated these days, and S. Singh of IBM Microelectronics.

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Given that the frequency response of state of the art SiGe HBTs has reached unprecedented levels, designers are now beginning to seriously attack microwave and even mm wave applications in SiGe. Tretiakov of RF Micro Devices. Liang of Georgia Tech. Groves IBM Microelectronics 4. C V AC Device Measurement Techniques: Overview Development of high quality device models is an essential ingredient in the design of successful analog and mixed signal applications.

Accurate device characterization plays a critical role in model develop ment and circuit benchmarking. Model behavior must be verified against device measurements in order to validate the model and to define regions outside which the model may be inaccurate. The characterization of high performance silicon heterostructures, and associated passives, requires care due to the demanding requirements associated with these devices: high frequencies, low leakage currents, low resistances, wide temperature ranges, etc.

An area of particular concern and interest to device modelers and circuit designers is the improvement of the S parameter measurement methodology as the measurement frequency extends to GHz and beyond. Traditional calibration and de embedding techniques need to be re examined to determine if the underlying assumptions remain valid [1,2]. In addition to characterization in support of model development, circuits must be measured and compared to design predictions and requirements.

Circuit measurement is particularly demanding for applications utilizing SiGe devices due to the high frequency and low noise characteristics of these designs [3,4]. Frequently, off the shelf measurement solutions do not exist to satisfy the characterization requirements for these cutting edge circuits, requiring circuit designers to assume the role of test system developer. Preceding all these requirements is the necessity to create carefully controlled device measurement test structures that allow for accurate extraction of the desired device and circuit parametrics.

Careful thought must be given to the limitations inherent in creating low parasitic test structures in a wafer probing environment. This includes the creation of additional test structures that allow for the accurate characterization of the test structure parasitics, so that the device characteristics can be accurately de embedded from the measured data [5,6]. Often the linear behavior of the DUT to a test signal is needed in order to characterize or model its behavior.

A test system that is able to accurately report the network parameters of an unknown linear network to an applied signal is required for these high frequency measurements. Some network parameters appropriate to characterization and modeling of silicon heterostructures, passives, and circuits are H parameters hybrid parameters , Y parameters admittance parameters , Z parameters impedance parameters , S parameters scatter ing parameters , and T parameters transmission parameters. Each of these network parameter sets describes the response of the DUT to a defined set of input conditions.

H parameters, for instance, are widely used to determine HBT device characteristics. They are useful for this purpose because the equations describing the H parameters can naturally be used to determine short circuit current gain or b in addition to other useful device parametrics. Network parameters are applicable generally to N port networks. Most applications of network parameters are limited to between two and four port networks. Since many circuits and devices have two well defined ports, two port networks are quite often the most useful in determining DUT characteristics.

The two port network shown in Figure 4. Under conditions of applied stimulus to one of the ports and defined termination of the other port, the response of the network can be characterized in terms of the voltage and current relationships observed at the ports. For a two port network, two equations completely define the network character istics as a function of the applied stimuli and measured voltages and currents and some constants of proportionality simply the network parameters themselves.

Similarly, the other three H parameters can be derived from physical measurements by simply applying the appropriate voltages and currents and setting one of the ports to either an open or short circuit condition as required by the definitions in Equation 4. A problem arises in applying this direct measurement technique at high frequencies. It is difficult to achieve perfect short or open circuits at the device terminals due to the parasitics associated with the connections between the measurement instruments and the device.

These parasitic capacitances, resist ances, and inductances combine to make the characteristics of open and short circuit connections strong functions of frequency. Therefore, a short circuit at one frequency may appear to be an open circuit at another, etc. This makes the broadband, direct measurement of many of the network parameters difficult. Another difficulty comes into play with active devices. Even if perfect broadband open and short circuits were achievable, silicon heterostructures may not be stable under conditions of open and short circuit termination of their terminals due to high gain and low parasitic resistances.

The solution to this dilemma is to make device measurements using a set of network parameters that make use of applied bias and termination conditions that are easily achievable at high frequencies and that lend themselves to stable device operation. S parameters satisfy these requirements. S parameters are defined similarly to the previously described network parameters except that the applied bias conditions are defined in terms of traveling voltage waves, rather than total voltages and currents, and the termination conditions are defined in terms of the characteristic impedance of the transmission lines supplying these traveling waves, rather than open and short circuits.

Figure 4. The traveling voltage wave incident on port 1 will generate a reflected wave traveling back toward the source due to impedance mismatch between port 1 of the DUT and the transmission line. In addition, some of the energy will be transmitted through the network to port 2 and travel down the transmission line toward the load impedance. A voltage wave will then be reflected from the load toward port 2 assuming that the load impedance is not equal to the characteristic impedance of the line , some of which will be transmitted back through the network and travel down the port 1 transmission line toward the generator where it will be either reflected or absorbed.

Further reflections occur as each of these reflected voltage waves encounter an impedance mismatch or discontinuity. This complex combination of forward and reflected waves on the transmission lines connected to ports one and two will generate standing voltage waves. Loss less transmission lines connect the DUT to the applied signal and load termination. This implies that the voltage wave is totally absorbed by a load impedance that is equal to the characteristic impedance of the transmission line.

Thus, the two load conditions that must be achieved in order to directly measure the four S parameters are as follows: 1. A load has been put in place of the generator of Figure 4. The circuit of Figure 4. These load conditions in a typical S parameter measurement system are equal to 50 V, since the transmission lines connecting the measurement instrument and the DUT are generally 50 V transmis sion lines. This condition is much easier to achieve over a broad range of very high frequencies and contributes to a more stable measurement environment for high gain devices.

Measuring the S parameters of a DUT, then, consists of measuring the complex voltage waves present at the DUT ports under the conditions of an applied voltage wave transmitted through a loss less transmission line toward one port and the termination of the other ports with a 50 V load for a 50 V measurement system. While this is simpler than achieving the requirements for directly measuring a set of network parameters defined in terms of total voltages and currents implying that perfect open and short termination conditions must be realized , there are still difficulties in achieving accurate meas urements representative of the conditions at the DUT ports due to nonideal measurement conditions.

For example, the transmission line connecting the measurement instrument and DUT has losses and may not have a Z0 of exactly 50 V, making it nonideal; reflections occur where cables, waveguides, or wafer probes connect to the measurement system and the DUT due to impedance mismatches; the 50 V load termination has frequency dependent behavior and is not exactly 50 V; the generator does not have a perfect 50 V impedance; the equipment required to sample and measure the incident and reflected voltage waves causes additional losses and distortions; when making on wafer measurements, the probe pads and transmission line launches introduce further errors.

The procedures used to extract the DUT port characteristics from the raw measured S parameters are called calibration and de embedding. Instrumentation The measurement of S parameters is most commonly performed using a test instrument called a vector network analyzer VNA. Fully automated VNAs, able to measure more than one port S parameters, typically contain switching elements that allow for either a signal or load to be applied to each port in turn enabling the measurement of the multiport S parameters with no manual intervention.

In addition, a means of calibrating out the parasitics associated with connecting the VNA to a DUT is generally provided as an internal procedure that can be implemented from the instrument front panel or through a network connection by a host computer. Calibration Since all voltage wave measurements must, of necessity, be made in the VNA itself, a means of accounting for the effects of the nonideal transmission lines and other parasitics, present between the VNA measurement transducers and the DUT ports is required.

In the simplest sense, VNA calibration makes use of the concept of a shifted reference plane to enable the direct measurement of the DUT port characteristics. The measurement reference plane defines the actual ports of the uncalibrated, measured S parameters and exists somewhere in the interior of the VNA itself. This implies that 16 error terms the S parameters of the four port matrix S 0 must be determined during calibration in order to fully describe the four port error network.

Once the 16 error terms are known, the DUT S parameters can be extracted from the measured S parameters using matrix manipulation. This means that the eight S parameters representing signal transmission through the network are equal in both the forward and reverse directions i. A reciprocal four port network, then, can be fully qualified with 12 error terms, since four of them will be redundant.

This is, in essence, how the standard VNA 12 term error model is derived [8]. Calibration consists of measuring known standards located at the DUT reference plane and then applying algorithms to determine the 12 error terms. Copyright , Agilent Technologies, Inc. Reproduced with permission of Agilent Technologies. Let the four port error network represent the environment between the VNA and the probe tips. Shift the reference plane to the probe tips followed by an additional step called deembedding that is designed to characterize and remove any additional parasitics that might exist between the probe pads and the DUT.

Shift the reference plane directly to the DUT ports by measuring standards at the end of the signal launches that exist between the probe pads and the DUT. Each approach requires that the 12 unknown error terms be determined to a great degree of accuracy. The first approach requires the additional determination of the parasitic behavior of the probe pads and transmission line launches connecting the probes to the DUT.

Determination of the error terms is done in a similar manner regardless of the desired location of the corrected reference plane. If the reference plane is desired to be at the probe tips method 1 , then the calibration standards may be realized either on wafer or on a separate calibration substrate.

In order to shift the reference plane directly to the DUT ports method 2 , the calibration standards must be realized on wafer, in close proximity to the DUT. There are several different techniques that can be used to achieve the desired reference plane shift, generally named according to the calibration standards required to achieve the calibrations [9,10]:. Requires accurate knowledge of actual characteristics parasitic inductance and capacitance of cal standards up to the highest frequency of operation.

Used successfully to 50 GHz and beyond, but sensitive to probe placement at higher frequencies, making measurement repeatability a problem. Typically used in applications where probes cannot be placed such that they are opposed Best Practice AC Measurement Techniques. Accuracy suffers in relation to SOLT cals [11]. Multiple different line lengths probe spacing variable required to provide broadband calibration i. Characteristic impedance of lines defines reference impedance of resulting S parameters.

Extending frequency range below 5 GHz requires excessively long transmission lines as cal standards and may sacrifice accuracy. Dispersion effects on the transmission line Z0 can limit effectiveness [12]. Thru delay and Match resistance must be known. Match reactance adjusted to achieve best calibrated open response.